(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a dual damascene pattern.
(b) Description of the Related Art
Recently, with a decreased design rule of a semiconductor device, the line width of interconnections becomes smaller, and accordingly, a copper (Cu) interconnection having relatively small resistance (Rs) is increasingly used.
In general, the copper interconnection is formed in a single or dual damascene process. The dual damascene process includes a case where a trench is first formed and a via hole is formed later (the so-called “trench first” method), and a case where a via hole is first formed and a trench is formed later (the so-called “via first” method).
In the latter case where the via hole is first formed and the trench is formed later, copper corrosion can occur due to damage to a nitride film on an underlying copper layer. In order to prevent such copper corrosion, there have been proposed complicated processes where a via hole is filled with photoresist or a bottom antireflective coating material when a dual damascene pattern is formed, in order to prevent nitride film damage.
Accordingly, there is a need for improvement of the dual damascene process for the purposes of simplification and increased yield.